Floating point look-ahead binary multiplication system utilizing two&#39;s complement notation for representing negative numbers



Jan. 13, 1970 F. A. WILHELM, JR., ET AL 3,489,888

FLOATING POINT LOOK-AHEAD BINARY MULTIPLICATION SYSTEM UTILIZING TWOS COMPLEMENT NOTATION FOR REPRESENT ING NEGATIVE NUMBERS ll Sheets-Sheet l Filed June 29, 1966 INVENTOR,

FREDERICK A.wII HELM JR.

BY ELLIOT NEsTLE ATTORNEY Jan. 13, 1970 F A, wlLHELM, JR., ET AL 3,489,888

ELOATING POINT Loox-AHEAD BINARY MULTIPLICATION SYSTEM UTILIZTNG Two's COMPLEMENT NOTATION EoR REPRESENTING NEGATIVE NUMBERS 1l Sheets-Sheet 2 Filed June 29, 1966 INVENTOR FREDERICK A. wrLHELM JR.

By ELLIOT NESTLE ATTORNEY Jan 13, 19.70 F. A. WILHELM, JR.. ET AL 3,489,838

FLOATING POINT LOOK-AHEAD BINARY MULTIPLICATION SYSTEM UTILIZING TWO' S COMPLEMENT NOTATION FOR REPRESENTING NEGATIVE NUMBERS ll Sheets-Sheet 3 Filed June 29, 1966 *warm INVENTOR. FREDERICK A.W|LHELM JR. BY ELLIOT NESTLE ATTORNEY Jan. 13, 1970 F. A. WILHELM, JR., ET AL 3,489,888

FLOATING POINT LOOK-AHEAD BINARY MULTIPLICATION SYSTEM UTILIZING TWO'S COMPLEMENT NOTATION FOR REPRESENTING NEGATIVE NUMBERS Filed June 29, 1966 ll Sheets-Sheet 4 R. IU RM om... MH

L V l E Nw... I AS KE mwN RT E wm RL FE Y B vgl ATTORNEY Jan. 13, 1970 F.A.w1LHELM, JR.. ET AL 3,489,888

FLOATING POINT LOOK-AHEAD BINARY MULTIPLICATION SYSTEM UTILIZING TWO'S COMPLEMENT NOTATION FOR REPRESENTING NEGATIVE NUMBERS Filed June 29, 1966 l1 Sheets-Sheet 5 ADD+ SUB Ilo INVENTOR.

H6 5,4 FREDERICK AwlLHELM JR.

. By ELLIOT NEsTLE am gATTORNEY Jan. 13, 1970 F. A. WILHELM. JR., ET AL 3,489,888

FLOATING POINT LOOK-AHEAD BINARY MULTIPLICATION SYSTEM UTILIZING TWO'S COMPLEMENT NOTATION FOR REPRESENTING NEGATIVE NUMBERS Filed June 29, 1966 ll Sheecs--Shee'fl 6 SHR 2 SUM SET (X-l) SUM RESET (X-l) l SUM RESET X SUM SUM SET RESET (X'f SUM SUM

SUMMER INVENTOR. FREDERICK A.w|LHELM JR.

BY ELLIOT NESTLE TTORNEY Jan. 13, 1970 F. A. WILHELM, JR., ET AL 3,489,888

FLOATING POINT LOOK-AHEAD BINARY MULTIPLICATION SYSTEM UTILIZING TWO'S COMPLEMENT NOTATION FOR REPRESENTING NEGATIVE NUMBERS Filed June 29, 1966 ll Sheets-Sheet 7 80d I? t ,80e SHRZ SHR2 ADD#` A009( SUE* SUQ* Ain-3) .Mn-2i l 82e SHRI sHRl "i f ADD* ADD* SUB* y SUB* A01-2) AT5-l5 sHRa 8 SHR2 /8 SUM SET(n-5)` SUM SET(n-2) 86d 86 SHRI f l /lod SHRI t e H06 SUM sauna) L s A01-L SUM s Mn) SET Acc (n n Acc Bl T Bl T (r1-I) (n) -x ee R A(n|) R A(n /BBd It /88e SHR2 SHR 2 ADD* ADD* SUB* SUB* IMU-3)* A(n2)* 90d 90e SHRI T' SHRI f f ADD* ADDll SUB* SUB* A(n2)* AUI-1)* 92d. 92e, sHRa *f SHR2 'f SUM RESET (r1-3) SUM RESET (r1-2) S SUM SUM f UM SHRI 1/94d SUM SET RESET SHR, `/Me SET RESET (n-I) (n-1) (n) (n) SUM RESET(n-2) SUM RESET T (n-2) OR(n-I) OR(n) OPER OPER REG REG (r1-l) OR(n-l)( (n) ORG( lid He INVENTOR.

FREDE RiCK lA.W| LHELM JR.

BY ELLIOT NESTLE 's ll l 'l A ATTORNEY Jan. 13, 1970 F. A. WILHELM, JR., ET AL 3,489,888

FLOATING POINT LOOK-AHEAD BINARY MULTIPLICATION SYSTEM UTILIZING TWOS COMPLEMENT NOTATION FOR REPRESENTING NEGATIVE NUMBERS 1l Sheets-Sheet 8 Filed June 29, 1966 .MNE

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INVENTOR FREDERICK A wILHELM JR. BY ELLIOT NESTLE ATTORN EY Jan. 13, 1970 F. A. WILHELM, JR., ET AL 3,489,888

FLOATING POINT LOOK-AHEAD BINARY MULTIPLICATION SYSTEM UTILIZING Two's COMPLEMENT NOTATION FOR REPRESENTING NEGATIVE NUMBERS Filed June 29, 1966 1l Sheets-Sheet 9 INVENTOR.

FREDERICK A. WILHELM JR. BY ELLIOT NESTLE ATTORNEY Jan. 13, 1970 F. A. WILHELM, JR., ET AL 3,489,888

FLOATING POINT LOOK-AHEAD BINARY MULTIPLICTION SYSTEM UTILIZING TWO'S COMPLEMENT NOTATION FOR REPRESENTING NEGATIVE NUMBERS Filed June 29, 1966 ll Sheets-Sheet lO CELL In) CELLIn-II ONE CELL COMPLEMENT SIGN CELL CELL TABLE I2C I2b 38 3o I2C SHIFT RIGHT O I O O oNcE v O I I l O O I |20 I2b 38 30 I2C TABLE I I 2 SHIFT RIGHT O O TWICE I O O O I I O I I I O I O I I O l O I I TABLE 3 I I O O SUBTRACT l I I I I O O O I I TABLE 4 ADD I O O O I O I I I (-I ls DEFINED As DoNT CARE 0R NoT RELEVANT ATTORNEY `Ian. 13, 1970 Filed June 29, 1966 BITS F. A. WILHELM, JR., 3,489,888 FLOATING POINT LOOK-AHEAD BINARY MULTIPLICATION SYSTEM UTILIZING TWOS COMPLEMENT NOTATION FOR REPRESENTING NEGATIVE NUMBERS ll Sheets-Sheet 11 PLIER PLIER PuER Pos; PLIER Pos. PUER NEG. NEG.Q(O) NEG.QI0) @In-l) om) QIO )*a oNE 0(0)*S oNE ONE*1 Two* oNE*,Twc. oNE ,Twc.

ADD RSHR2 Anna SHR2 O o SHR 2 RESET oNE SHR 2 SET oNE SHR 2 o l ADD a SHR2 SHRI ADD a SHR2 SHR a Anm S SHR2 SET oNE SET Twc.

o SHR I Sua SHRI SUB sHR| `zal SHR2 a SHR2 sus Sua SUB I a SHR2 SHR2 a SHR2 SHR 2 S SHR 2 SET oNE SET Twc. RESET oNE SHR 2 SHIFT RIGHT TwlcE SHR| SH|FT R|GHT oNcE Il /0 INVENTOR.

FREDERICK A WILHELM JR. BY ELLIOT NESTLE ATTORNEY United States Patent O FLOATING POINT LOOK-AHEAD BINARY MULTI- PLICATION SYSTEM UTILIZING TWOS COM- PLEMENT NOTATION FOR REPRESENTING NEGATIVE NUMBERS Frederick A. Wilhelm, Jr., Eatontown, and Elliot Nestle, Neptune, NJ., assignors to Electronic Associates, Inc., Long Branch, NJ., a corporation of New Jersey Filed June 29, 1966, Ser. No. 561,575 Int. Cl. G06f 7/38 U.S. Cl. 23S-164 12 Claims ABSTRACT OF THE DISCLOSURE A floating point two bit look-ahead binary multiplication system using twos complement notation for representing negative numbers is disclosed by providing an' accumulator, a Q register, an operand register, a summer and multiply control circuitry. The control circuitry generates signals indicative of the proper action to be taken by the multiplication system. Any one of four operations may be performed; shift right twice; add and shift right twice; subtract and shift right twice; and shift right once. By proper choice of these operations corrections for a negative multiplier is accomplished resulting in a correct product.

This invention relates to a ltwos complement multiplication system for a digital computer and more particularly to a floating point multiplication system utilizing two bit look-ahead circuitry.

Twos complement floating point multiplications systems for digital computers are known in the art. -In many such systems the time for multiplication may be substantially reduced by looking at more than one bit of the multiplier or multiplicand at one time. In this manner multi-bit look .ahead has been used to achieve rapid multiplication. In such multiplication positive numbers or negative numbers or any combination thereof may be multiplied together to produce an algebraic product. However, prior multiplication systems using negative numbers required complex control circuits as a result of inherent ambiguities. These ambiguities arise because the algorithm used in twos complement multiplication is required to differentiate in the multiplier bits between a magnitude or a magnitude 1. Without a past knowledge of data it is impossible to determine the magnitude of a given bit of a twos complement string.

Some prior multiplication systems have converted all negative multipliers to their positive equivalents thereby effectively circumventing the above problem. However such prior systems have required fix-up cycles at the end of the multiplication to provide correction and this has resulted in a substantial increase in the multiplication time. Other prior multiplying systems have effectively complemented the binary information applied to multiplying control circuitry which required a substantially larger amount of logic circuitry.

Accordingly an object of the present invention is a twos complement multiplication system which when operating upon negative multipliers does not require any physical complementing of the multiplier.

Another object of the present invention is a twos complement multiplication system which does not require any effective complementing of the binary information `applied to the multiply control circuitry.

In accordance with the present invention there is provided twos complement multiplication system for a digital computer having an accumulator, a Q register,

3,489,888 Patented Jan. 13, 1970 an operand register, a summer and multiply control circuitry. T'he signals indicating the action to be taken by the multiplication system are generated by the multiply control circuitry. The decisions of the control circuitry are modified to correct for the singularities of the negative multipliers. Specifically, any one of four operations may be performed, e.g. shift right twice, add and shift right twice, subtract and shift right twice and shift right once. By proper choice of any one of these operations, corrections for any negative multiplier will result Ain a correct product.

In this manner substantially less circuitry is required to perform the desired multiplication as compared with prior multiplication systems which effectively complemented the binary information applied to the control circuitry. In addition the system according to the invention provides substantially more rapid multiplication than the prior systems which physically complemented the multiplication.

For further objects and advantages of the invention and for a more detailed discussion of its component parts and the manner of operation, reference is to be had to the following description taken in conjunction with the accompanying drawings in which:

FIG. 1 is a block diagram of a multiplying system illustrating the invention;

FIGS. 2 and 3 are block diagrams of control circuit gates;

FIG. 4 is a block diagram of the summer and the timing system;

FIGS. 5A, 5B and 6 taken together are block diagrams of a representative portion of the accumulator;

FIGS. 7 and 8 taken together are block diagrams of a representative portion of the Q register; and

FIGS. 9 and 10 are tables to show the operation of the gates of FIGS. 2-8.

Referring now to FIG. 1, there is shown a multiplication system for positive and negative oating point numbers comprising a signed mantissa and a signed exponent.

GENERAL DESCRIPTION The multiplication system includes an accumulator register 10 in which the most significant half of the product will reside after the multiplication is completed. In addition, register 10 operates as a working register storing and manipulating the partial product. Further, an operand register 11 and a Q register 12 are provided. Registers 10-12 each include a plurality of binary cells each of one binary digit capacity. The number of cells in each of the registers 10-12 are equal and in a specific embodiment may be equal to twenty-three cells plus a Sign cell.

In this description in binary terminology a l-state corresponds to a logic high and a O-state corresponds to a logic low. The complement notation will be used, e.g. ADDl. In addition the following is a partial list of terms that are used in the description:

Stringtwo or more successive cells t Sum-algebraic addition or subtraction between the accumulator register 10 and operand register 11.

The multiplier initially resides in the Q register 12 with the least significant cell indicated in FIG. 1 as cell n (12a) and the next most significant cell as cell n-l (12b). The outputs of cells n and n-1 together with the most signicant cell 12C of the Q register are applied as inputs to a multiply control circuit 15. On the basis of these inputs, circuit 1S generates control signals which are applied by way of conductors 15a to register 10, conductors 15b to register 12 and conductors 15e` to a summer 18. Summer 18 has applied thereto inputs from register 11 by way of conductors 19 and inputs from register by way ofrconductors 20. Summer 18, based on the inputs received from registers 10v and 11 and circuit 15, generates signals which represent the algebraic sum or difference of registers 10 and 11 and applies these signals to register 10 by way of `conductor 18a and to a part of register 12 by way of conductor 1'8b.

The multiplicand resides in operand register 11. Depending on the state of cells n and n-l and the sign cell of the Q register 12, control circuit 15 develops any one or combination of the 'following signals to operate the summer 18 and/or gates in register `10 and register 12. Specifically, these signals indicate:

shift right twice (SHR 2) shift right once (SHR 1) add (ADD) subtract (SUB).

and the complements of each of the above signals.

The foregoing basic multiplication system is described in the literature, as for example in the text by Ivan Flores, The Logic of Computer Arithmetic, Prentice-Hall, 1963 at page 193 et seq. As described in the text, on the basis of the state of cells n and n-l the signal from circuit 15 causes a partial product to be developed in register 10 and part of register 12. The partial product is a function of the contents of registers 10 and 11 and cells n and n-l and the sign cell of register 12. In forming the first partial product the contents of the information state of register 10 is shifted right once or twice. Thus the information from the least significant cell or cells shifts into the most significant cell of Q register 12. Similarly, the contents of the information states of Q register 12 is shifted once or twice. The shifting of registers 10 and 12 is dependent on the output of control circuit 15, later to be described in detail.

As a result of this shifting of the contents of cells n and n-l (12a, 12b), the contents of these cells may change and the new contents represent the next multiplier bits to be applied to or scanned by circuit 15. In similar manner, a second partial product will be formed and the multiplier in the Q register 12 is again shifted to scan successive bits.

When the complete multiplier, formerly residing in Q register 12, has been scanned the partial product now residing in accumulator register 10 and all of register 12 represents the complete product. The most significant half of that complete product will reside in register 10 and the least significant part in register 12. There has now been described the generation of the mantissa of the product. In addition, the exponents must be added to produce the correct exponent of the product. Specifically, the exponent of the multiplicand resides in operand exponent register 24 and the exponent of the multiplier resides in the accumulator exponent register 26. These two exponents are added by exponent adder 28, with the resultant sum being stored in register 26.

The operation of control circuit 15 and the manner in which it manipulates positive multipliers in the multiplier system is well known in the art and is described for example in the above cited'textat page 201 et seq.`ln accordance with the invention, circuit 15 manipulates negative multipliers to produce multiplication in which there is achievedv a good balance between .cost of the associated circuitry and the speed of multiplication. i

MUITIPLY CONTROL rCIRCUIT FOR MANIPULA- HON .OFINEGATIVE MULTIPLIERS,

f The .multiply control circuitl 15 of FIG. l 'comprises the gatingl circuits of FIGS. 2 and 3. `In FIGjZ there is Shown a complement flip-flop (TWC) 30 of the type well known in the art, having a set and a reset input and a 1',side and a 0side output. Hereinafter ip-flops nr binary cells may be anyone of the well known types having two stable states in which, in its l-sta-te, the l-side is highand the 0-side is low.

The set input of flip-flop 30 is connected to an output output of cell n (12a) and'sign cell 0 (12C) of the Q register 12. In addition a timing pulse t, later to be described in detail, is also applied to gate 31. Thus cell 30 is set to its l-state when cell n-and the sign cell are high and a timing pulse is applied all in coincidence.r It will be understood that cell 30 is initially reset by a start signal in coincidence with a timing pulse, bothapplied to. AND"'gate, 32, the, output of which is connected to the reset terminal of cell 30.V

It will be understood that for the purpose of this description only negative multipliers are involved so that the sign cell 12C of register 12 is always in a l-state. Thus when gate 31 `is enabled by signal Q(n), this indicates a l-state of the multiplier resides in cell n of register 12. At the time of the timing pulse, with all inputs high, gate 31 applies a pulse to set cell 30 in its l-state. This indicates that the absolute magnitude of the remaining multiplier is the twos4 complement of the states of the binary cells of the remaining bits in the multiplier then residing in register 12. I

IFlip-flop or binary cell 38 is defined as the onep fiipop and is initially reset by a'start signal in coincidence with a timing pulse both of which are applied to AND gate 39 connected to the reset terminal offlp-flop 38. The output of AND gate 36 is also connected to the reset terminal and has as its inputs the l-sides of cells 12a and 12b, cell 38, and cell 30.1AND gates 34 and 35 have outputs connected to the set terminal of flip-flop 38. The inputs of gate 34 are the l-sides of cells 12a and 12C and the 40sides of cells 12b, 38, and 30. In addition the inputs of gate 35 are the 0sides of cells 12a, 12b, 38 and the 1side of flip-fiop 30. The one flip-flop or binary cell 38 signifies that a string of ones in cells n and n-l (12a, 12b) are in the process of being scanned. A string of ones may be defined as a string (two or more) of (l-states passing through'cells 12a and. 12b if a l-state in these cells has' previously been recognized (gate 35). Flip-flop 30 operates as a history of the l-states passing through cells 12a which causes it to switch to the l-state. In addition a string of ones is defined as a l-state passing through cell 12a and a O-state passing through gate 12b if a 1-state in these cells has not previously been recognized (gate 34). That is, llip-fiop 30 has not been set to a l-state.

AND gate 36 operates to reset flip-fiop 38 when a string of ones is no longer recognized (or scanned). Thus, liip-op 38 is set when a string of ones is recognized by gates 34 and 35 or reset when a string of ones has been terminated.

Referring now to FIG. 3, there is shown a generation of signals shift right twice (SHR 2) and shift right once (SHR 1). AND gates 45, 46, and 48 are associated with the SHR 1 signal and have their outputs connected together as a virtual OR to provide the SHR 1 output. Gate45 has applied thereto the l-sides of cell 12b and the 0sides of cells 12a, 38 and 30. Gate 46 has applied thereto the l-sides of cells 12b, '120, 38, and 30 and the 0-side of cell 12a. Further, gate 48 has applied thereto thev 1-sides of cells 12a, 12C and 30 andthe 0sides of cells 12b and 38. It will be understood by those skilled in the art that gates 45, 46 and 48 are defined by the truth table 1 illustrated in FIG. 9. Signal SHR 1 in conjunction with other signals later to be described causes either of (1) the information states of registers 10 and 12 to be shifted 1 position to the right in the direction of lesser magnitude, or (2) the output of summer 18 to gate its information to the proper gates of register 10 and the most significant bit of register 12. The choice of (1) 'or (2) depends on the signals ADD and SUB which will later be defined.

AND gates' 50, 52, 54, 56 and 60 are associatedI with l the signal SHR 2 and have their Youtputs connected together as a virtual OR to provide the SHR 2 output.

,Gate 50 has applied thereto the l-sides of cells 12a and 12b. Gate 52 has applied thereto the 0-sides of cells 12a and 12b. Gate 54 has applied thereto the l-sides of cells 12a and 12C and the O-sides of cells 12b, 38, and 30. Further, gate 56 has applied thereto the l-sides of cells 12a, 38, 30, and 12C and the (l-side of cells 12b. In addition the gate 60' has applied thereto the l-sides of cells 12b, 30, and 12e and the O-sides of 12a and 38. Thus it will be understood that gates 50, 52, 54, 56, and 60 are defined by the truth table 2 illustrated in FIG. 9. The signal SHR 2 in conjunction with other signals' causes either (1) the information states of registers and 12 to be shifted two positions to the right in the direction of lesser magnitude or (2) the output of summer 18 to gate its information through the proper gates of register 10 and the two most significant bits of register 12. The choice of (l) or (2) depends on the signals ADD and SUB.

In FIG. 3 subtract signals (SUB) are generated by AND gates 62, 64, and 66 having their outputs connected together as a virtual OR to produce the SUB signal. Specifically, gate 62 has applied thereto the l-sides of cells 12b, 30, and 12C, and the O-sides of 12a and 38. Gate 64 has applied thereto the l-sides of cells 12a and 12b and the 0-sides of cells 38 and 30. In addition gate 66 has applied thereto the l-sides of cells 12a, 12b, 12C, 38, and 30. Accordingly, gates 62, 64, and 66 may be defined by the truth table 3 of FIG. 9. The subtract signal in conjunction with SHR 2 causes the summer 18, FIGS. 1 and 4, to develop signals sum set and sum reset which are applied to the proper cells of registers 10v and the two most significant cells of registers 12.

Signals ADD are generated b'y AND gates 70, 72 and 74 the outputs of which are connected together to produce the ADD signal. Specifically gate 70 has applied thereto the l-sides of cells 12C and 30 and the O-sides of cells 12a and 12b and 38. Gate 72 has applied thereto the l-side of cell 12a and the 0i-sides of 12b, 30, and 38. Gate 74 has applied thereto the 1sides of cells 12a, 12C,

30, and 38 and the O-side of cell 12b. Accordingly the t gates 70, 72 and 74 may be defined by truth table 4 of FIG. 9. The ADD signal in conjunction With SHR 2 causes the summer 18, FIGS. 1 and 4, to develop the signals sum set and sum reset which are applied to the proper gates of register 10 and the two most significant bits of register 12. Gates 70, 72, and 74 are defined by table 4, FIG. 9.

OPERATING REGISTERS The differing outputs of the circuits shown in FIGS. 2 and 3 comprising the multiply control circuit 15, FIG. l, are applied to the operating registers illustrated in FIGS. 5-8. FIGS. 5 and 6 show the logic and binary cells or flipiiops of the accumulator register 10 and FIGS. 7 and 8 taken together show the logic flip-flops of the Q register 12. Only five binary cells have been illustrated for accumulator 10 and only four cells for Q register 12 though it will be understood that any number of cells may be provided. The only requirement is that there must be as many cells in each register as there are bits in the multiplier, as for example in one embodiment twenty-three bits.

FIG. 5 illustrates `any general consecutive binary cells 10a-10c of register 10 and FIG. 6 illustrates the two least significant cells n and n-l (10d, 10e respectively). FIG. 7 illustrates in the Q register 12 the two most significant bits 12d (most significant) and 12e (next most significant). In addition, FIG. 8 shows in the Q register the two least significant bits, cell n (12a) and cell n-l (12b).

With regard to FIGS. 5 and 6 it will be understood that the corresponding elements of the different stages 10a- 10e of accumulator 10 have been identified by the same reference character plus a suffix corresponding to that particular stage. Since all of the binary cells of accumulator 10 are similar, only one of them, cell or flip-iiop 10c will be described in detail. Associated with cell 10:,` is logic circuitry having inputs identified by a corresponding mnemonic. This logic circuitry comprises (l) AND gates C, 82C, 84C, and 86C, the outputs of which are connected together and applied to the set side of flip-flop 10c and (2) AND gates 88C, 90C, 92C and 94C the outputs of which are connected together and applied to the reset side of that iiip-iiop. Accordingly, each of the four AND gates connected to the set side has a corresponding complementary term AND gate connect to the reset side. In this manner a selected binary cell of register 10 always takes a predetermined state for each applied timing pulse.

If circuit 15 generates high signals SHR 2, ADD*, and SUB*k then gates 80e and 88C are partially enabled. Thus the command is to shift right twice and therefore the information state of a binary cell of the accumulator 10, two bits more significant than cell 10c, i.e. cell 10a, should be shifted into cell 10c. It Will be noted that one of the inputs of gate 80C is the l-side of cell 10a While one of the inputs of gate 88e is the 0-side of cell 10a. Accordingly, if the state of cell 10a is in a l-state then gate 80a` is totally enabled and gate 88C is disabled. Thus in coincidence with the timing pulse, cell 10c is setto its l-state. It will here be noted that there is a gate equivalent to gates 80e and 88e associated with each of the cells 10a- 10c as well as 12d, and 12e.

As a result of the signal SHR 2 the binary states of the registers 10 and 12 will have been effectively shifted right twice. The information state of the sign bit of accumulator 10 (not shown) will shift through the first to the second most significant cell of that register. However no information is shifted into the sign cell 12C.

In manner similar to that described above, if circuit 15 generates l-state signals SHR 1, ADD* and SUBt, then gates 82e and 90e are partially enabled. These gates are effective to shift the information states of register 10 one position to the right in the direction of lesser significance. It will be noted that the l-side of flip-flop 10b is connected to an input of gate 82C and the 0-side of Hip-flop 10b is connected to an input of gate C. Therefore depending on the state of flip-flop 10b, either gate 82C or 90C will be totally enabled. Upon coincidence of a timing pulse cell 10c is set or reset in accordance with inputs to gates 82C or 90C.

Similar gates are provided for logic circuits associated with the cells of registers 10 and 12 which produce the complete shift. If circuit 15 produces (l) a l-state SHR 2 and (2) a l-state ADD or a l-state SUB, then gates 84C and 92a` will be partially enabled. It will be seen that a l-state ADD or SUB are applied to summer 18 to develop a sum set and a sum reset signal, later to be describe-d in detail. The summer 18 may produce a lstate signal to be applied to the sum set input of gate 84C or a l-state signal to be applied to the sum reset input of gate 92C. It will be understood that sum signals represent the information set of an algebraic addition or subtraction of the accumulator and operand bits two positions in the direction of greater significance, e.g. cells 10a and 11a.

In coincidence with a timing pulse, cell 10c assumes an information state corresponding to the algebraic sum of cells 10a and 11a. The shifted sum is applied to all of the cells of register 10 and to the two most significant cells of register 12, viz. cells 12d and 12e. The algebraic sum of the accumulator and operand sign bits (not shown) is shifted into the two most significant bits of accumulator 10. A description similar to the above is applicable to gates 86e and 94C, the only difference being that the algebraic sum is shifted only once in the direction of least signicance. l

Referring now to FIGS. 7 and 8, illustrating register 12, the most significant bit of that register, viz. cell 12d, includes logic similar to that of accumulator 10. The logic of cell 12e (the next most significant cell) is similar to the logic of cell 10c except that there is absent a gate corresponding to gate 86cand its complement gate 94C. The reason for this absence is that the action signal corresponding to gates 86e and 94e is a sum and shift once which will be generated only as far as cell 12d. Instead gates 111e and 112e are provided having as input signals SHR 1, and the l-side and -side of cell 12d, respectively. Therefore in coincidence with the timing pulse, cell 12e copies the information state of cell 12d.

Cells 12d and 12e serve as an extension to accumulator 10. For example, when shifting right twice, the information state of cell d of the accumulator is shifted to cell 12d of the Q register. The state of cell 10e is shifted to cell 12e. Thus it will now be clear that the Q register cells of lesser significance than 12e, e.g. 12a and 12b, do not contain sum set and sum reset gates 84C and 86C, 92C and 94C since the sum can only be shifted twice and cannot extend into the cells of less significance than cell 12e of the Q register 12.

Cells 12a and 12b always copy the information states of the preceding cell for the SHR 1 command and will copy the information states of a cell two bit positions more significant -for an SHR 2 command. During multiplication it will be understood that either of the signals SHR 1 or SHR 2 must be high. For example, the SHR 1 signal is applied to gates 111a and 113a and the l-side of cell 12b is applied to gate 111g. In addition the O-Side of cell 12b is applied to gate 113a. Thus if signal SHR 1 and the l-side of cell 12b are high, then cell 12a is set on a time pulse thereby copying the information state of cell 12b. There has now been explained the way in which the operating registers function to perform binary multiplication using a negative multiplier.

MACHINE TIMING The timing system 21, as shown in FIG. l, has applied thereto the signals SHR 1 and SHR 2 and produces the timing pulses t which are applied to circuit 15 and registers 10-12. Timer 21 is shown in detail in FIG. 4 and comprises a source of clock pulses 150 and a down counter register 152 of the type well known in the art, as for example as described in the book, Digital Computer and Control Engineering by R. S. Ledley, McGraw- Hill Book Co., 1960 at page 488 et seq.

In operation of the timing system, signals SHR 1 and SHR 2 and a start signal (generated externally) are applied to the timer. Specifically, SHR 2 is applied to AND gate 154 the other input of which is the source of timing pulses t. In addition signal SHR 1 is applied to AND gate 156 in conjunction with the signals t. The outputs of gates 154 and 156 as well as the output of a gate 160 are applied as inputs to counter 152. It will be seen that the input to AND gate 160 is a start signal. The output of counter 152 is the timing pulse which is applied to registers 10-12 and circuit 15, for machine timing later to be described in relation to machine operation.

In particular operation of timer 21, signal SHR 2 in a l-state in conjunction with a timing pulse t causes counter 152 to decrement by two and generate a timing pulse t(n) to the machine. Similarly SHR 1 in a l-state in conjunction with a timing pulse t causes counter 152 to decrement by one and generate a timing pulse t(n). When counter 152 is completely reset to its initial state, the machine timing pulses t(n) will be disabled.

SUMMER 18 Summers used with multiplication systems are Well known in the art and are set forth in the above cited Ledley text in Chapter 6. The known summers may be modified in the manner shown in FIG. 4 to provide a summer used in the present embodiment. Summer 18 produces either a signal sum set or ysum reset which either sets or resets a desired cell of registers 10 or 12 as a function of the arithmetic instructions ADD, SUB, carries and operand content. For example, Q register cell 12e, FIG- URE 7, is set by signal sum set (n) if gate 170, FIGURE 4, is enabled by signals ADD, OR(n) A(n)* and carry C(n-1). Generation of these carries are fully described in the cited Ledley text, Chapter 6. It will be understood that only the summer circuit for one bit position (n) has been illustrated and there is provided a similar circuit for each of the remaining bit positions of the multiplication system of the present invention.

OPERATION OF SYSTEM There will now be described a typical operation of the multiplication system using a negative multiplier. For this example it will be assumed that registers 10-12 each have a length of ten binary cells including a sign cell representing the mantissa. The exponents of the `operands will be a ffour bit signed (with sign) binary number residing in registers 26 and 24.

Accumulator 10 has been preset to the state in which all cells are in a 0state and the multiplier resides in register 12 and the multiplicand resides in register 11. Thus the contents of register 12 at any given time is illustrated in the drawings as (Q). The contents of accumulator 10 is illustrated as (A); and the contents of the operand register 11 is illustrated as (OR). In operation, timer 21 is initially set to the number of bits of the multiplier neglecting the sign bit which in the assumed condition is nine bits. On the multiply command, a high start signal is applied to an input of AND gate 200, FIG. 2, which produces a signal ADD EX. This signal is applied to exponent adder 28, FIG. l. In addition the start signal is applied to the timing system 21 to set the `down counter 152 to the multiplier count which in the assumed example will be a count of nine. Thus it Will be understood that at time t9, the first cycle of multiplication, the register contents are as follows:

(l) (A) 0.000000000 (Q) l.llOOlll(00) It will be noted that the bits within the parentheses represent the states of cells 12a (Qn) and 12b (Qrr-l) connected to control circuit 15. At time t9, as a result of the states of cells 12a and 12b, the following signals are in a l-state:

Control circuit 15 has called for a signal SHR 2 and the decrementing of down counter by two. In coincidence with the termination of pulse t9 the signal ADD EX causes the contents of registers 24 and 26 to be added by exponent adder 28 with the final result placed in register 26. The accumulator exponent register 26 now holds the sum of the two operand exponents.

Further at the termination of time t9, the contents of registers 10 and 12 are shifted right twice and the down counter decremented by two so that at time t7 the register configuration is:

(3) (A) 0.000000000 (Q) l.00)ll00l(1l) It will now be understood that the following signals are in `a l-state:

(4) ONES, TWC, Q(n-l), Q(n), SHR 2 SUB (5) (A) 1.111000000' (Q) 1.0000)ll0(0l) The signals now in a 1-state are Q(/t-.-l)*, Q(n),

9 TWC, ONEl, SHR 1, SUB*, ADDl. Thus a shift right once and a decrementing of the down counter by one is being called for. In coincidence with the end of time t5, the contents of registers and 12 are shifted one position to the right so that at time t4:

The signals now in a l-state are Q(n1)*, Q(n)*, TWC, ONE*, ADD, SHR 2. In addition gate 35 is enabled to set the ONE fiip-fiop 38. In addition the timing system is decremented by two. In coincidence with the termination of time i4, the contents of register A (10) is added to register 11 and shifted right twice and the ONE flip-flop is set. Thus at time t2:

At this time the signals in a l-state are:

(8) Q01-1), Q(n), ONE, TWC, SUB, SHR 2 In this manner a subtract and a shift right twice are called for and a timing system decremented by two. In coincidence with the end of time t2, the registers contain:

Since the down counter of system 21 is now at zero, this signifies completion of the multiplication. The data in register 10 is the most significant half of the product and the data in register 12 is the least significant half of the product. In order to prove that the answer in expression (9) is correct, the following steps may be taken:

(10) TWOS COMPLEMENT OF PRODUCT- (11) MULTIPLICAND 0.100000000= -i-Z- (12) TWOS COMPLEMENT OF MULTIPLIER- (001100100) (2-3-i-2`4-l-2-7) (14) (Expression 13) (Expression 10) Thus, in accordance wih the invention there is provided a multiplication system in which the decisions ofcontrol circuit 15 are modified to correct for the singularities of negative multipliers as summarized in Tables 1-4, FIG. 9, and further defined in FIG. 10.

While the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.

What is claimed is:

1. A floating point two bit look-ahead binary multiplication system using twos complement notation for representing negative numbers, comprising an accumulator register, a Q register and an operand register each having the same number of binary cells and each including a binary cell corresponding to a sign bit, the multiplier residing in the Q register and the multiplicand residing in the operand register, cell n being the least significant cell of said Q register and cell ni-l being the next most significant cell of said Q register,

an exponent accumulator and an exponent operand register each having the same number of binary cells and each including a binary cell corresponding to a sign bit, the exponent of the multiplier residing in the exponent accumulator register and the exponent of the multiplicand residing in the exponent operand register, an exponent summer having inputs connected to each cell of said exponent accumulator register and exponent operand register and, means connected to said exponent summer for applying the resultant to the exponent accumulator register,

a summer having inputs connected to each cell of said accumulator register and operand register and operable for summing in parallel the binary information in said accumulator and operand register and, means connected to said summer for applying the resultant to said accumulator register and to the two most significant cells of said Q register,

a twos complement binary cell connected to said sign cell and said cell n of said Q register whereby said complement cell is set to its 1state when both said sign cell and said cell n are in a 1state,

a one binary cell connected to said sign cell, cell n, cell nt-l of said Q register and said complement cell whereby,

( 1) said one cell is set to a 1state when (a) said sign cell and cell n are in a l-state and cell nr-l and complement cell are in a 0-state, or (b) said complement cell is in a l-state and said cell n and cell n-l are in a O-state, (2) said one cell is reset to a 0-state when said cell n, cell m-l and complement cell are in a l-state, add gate means having inputs connected to said sign cell of said Q register, cell nr- 1, cell n, one cell and complement cell and having outputs connected to each of the cells of said accumulator register, the two most significant cells of said Q register and to said summer for adding the binary information in said accumulator register and operand register when (1) said cells n and n-1 and one cell are in a 0- state and said complement cell and said sign cell are in a l-state, or (2) said cell r`11, one cell and complement cell are in a O-state and cell n is in a l-state, or (3) said cell n, one cell, complement cell and sign cell are in a l-state and cell r11-1 is in a 0-state.

2. The multiplication system of claim 1 in which there is provided subtract gate means having inputs connected to said sign cell of said Q register, cell n-l, cell n, one cell and complement cell and having outputs connected to each of the cells of said accumulator register and the two most significant cells of said Q register and of said summer for subtracting the binary information in said accumulator and operand registers when (l) cell nl-l said complement cell and said sign cell are in a 1state and cell n, and one cell are in a 0- state, or

(2) cell n and n-l are in a 1state and one cell and complement cell are in a O-state, or

(3) all of said cells are in a l-state.

3. The multiplication system of claim 1 in which there is provided shift right twice gate means connected to each of the binary cells of said accumulator and said Q register for producing a signal to shift the information state of the accumulator register and of the Q register or the information state from the summer two bit positions to the right in the direction of least significance when 1) cells n and nl-l are both in a O-state or both in a l-state, or

(2) cell n and said sign cell are in a 1state and said cell n-l, complement cell and one cell are in a 0- state, or

(3) cell n-l, said complement cell and said sign cell are in a l-state and said cell n and one cell are in a O-State, or

(4) cell n, said one cell, said complement cell and said sign cell are all in a 1-state and cell n-l is in a 0- state.

4. The multiplication system of claim 1 in which there is provided shift right once gate means connected to each of the binary cells of said accumulator and said Q register for producing a signal to shift the information state of the accumulator and Q register or the information state of the summer one bit position to the right in the direction of least significance when (1) cell n', said complement cell and said sign cell are in a 1-state and cell m-l and one cell are in a tl-state, or

(2) cell n, one cell and complement cell are in a 0-state and cell nl-l is in a l-state, or

(3) cell n-l, one cell, complement cell and said sign cell are in a l-state and cell rn is in a -state.

5. In a digital computer a floating point two bit lookahead multiplication system using twos complement notation for representing negative numbers, comprising an accumulator, a Q register and an operand register each `having the same number of binary cells and each including a binary cell corresponding to a sign bit, the multiplier residing in the Q register and the multiplicand residing in the operand register, cell n being the least significant cell of said Q register and cell n-l being the next most significant cell of said Q register,

an exponent accumulator and an exponent operand register each having the same number of binary cells, an exponent summer having inputs connected to each cell of said exponent accumulator and exponent operand register and, means connected to said exponent summer for applying the resultant to the eX- ponent accumulator,

a summer having inputs connected to each cell of said accumulator and operand register and operable for summing in parallel the binary information in said accumulator and operand register and, means connected to said summer for applying the resultant to said accumulator register and to the two most significant cells of said Q register,

a twos complement binary cell connected to said sign cell and said cell n of said Q register whereby said complement cell is set to its l-state when both said sign cell and said cell n are in a l-state,

a one binary cell connected to said sign cell, cell n, cell n-1 of said Q register and said complement cell whereby,

(l) said one cell is set to a l-state when (a) said sign cell and cell n: are in a 1state and cell n-l and complement cell are in a 0- state, or (b) said complement cell is in a 1state and said cell n and cell nl-l are in a 0-state (2) said one cell is reset to a (l-state when said cell n, cell n-l and complement cell are in a lstate, and

substract gate means having inputs connected to said sign cell of said Q register, cell n-l, cell n, one cell and complement cell and having outputs connected to each of the cells of said accumulator register and the two most significant cells of said Q register and of said summer for subtracting the binary information in said accumulator and operand register.

`6. The multiplication system of claim in which there is provided a plurality of shift right twice gates connected to each of the binary cells of said accumulator and said Q register and to said one and complement cells for producing a signal to shift the information state of the accumulator and of the Q register or the information state from the summer two bit positions to the right in the direction of least significance when (l) cells n and ni-l are both in a 0state or both in a 1-state, or

(2) cell n and said sign cell are in a 1state and said cell n-l, complement cell and one cell are in a 0- state, or

(3) cell nl-l, said complement cell and said sign cell are in l-state and said cell n and one cell are in a 0-state, or

(4) cell n, said one cell, said complement cell and said sign cell are all in a l-state and cell n-1 is in a 0- state.

7. The multiplication system of claim 5 in which there l2 is provided a plurality shift right once AND gates connected to each of the binary cells of said accumulator and said Q register for producing a signal to shift the information state of the accumulator and Q register or the information state of the summer one bit position to the right in the direction of least significance. i

8. The multiplication system of claim 7 in which ther is provided add gate means having inputs connected to said sign cell of said Q register, cell n-l, cell n, one cell and complement cell and having outputs connected to each of the cells of said accumulator register, the two most significant cells of said Q register and to said summer for adding the binary information in said accumulator register and operand register.

9. The multiplication system of claim 7 in which there is provided shift right twice gate means connected to each of the binary cells of said accumulator and said Q register and to said one and complement cells for producing a signal to shift the information state of the accumulator register and of the Q register or the information state from the summer two bit positions to the right in the direction of least significance'.

10. The multiplication system of claim 9 in which there is provided a plurality of add gates having inputs connected to said sign cell of said Q register, cell n-1, cell n, one cell and complement cell and having outputs connected to each of the cells of said accumulator register, the two most significant cells of said Q register and to said summer for adding the binary information in said accumulator register and operand register when (l) said cells n and n-l and one cell are in a 0-state and said complement cell and said sign cell are in a a 1state, or

(2) said cell nf-l, one cell and complement cell are in a (l-state and cell m is in a l-state, or

(3) said cell n, one cell complement cell and sign cell are in a l-state and cell n-l is in a 0-state.

11. A binary multiplication systemy using twos complement notation for representing negative numbers, comprising an accumulator, a Q register and an operand register each having the same number of binary cells and each including a binary cell corresponding to a sign bit the multiplier residing in the Q register and the multiplicand residing in the operand register cell n being the least significant cell of said Q register and cell n-l being the next most signicant cell of said Q register,

an exponent accumulator and an exponent operand register each having the same number of binary cells and each including a binary cell corresponding to a sign bit,

a summer having inputs connected to each cell of said accumulator register and operand register and operalble for summing in Iparallel the binary information in said accumulator and operand register and, means connected to said summer for applying the resultant to said accumulator and to the two most significant cells of said Q register,

a twos complement binary cell connected to said sign cell and said cell n of said Q register whereby said complement cell is set to its 1state when both said sign cell and said cell n are in a l-state,

one binary cell connected to said sign cell, cell n, cell n-l of said Q register and said complement cell whereby,

(l) said one cell is set to a l-state when (a) said sign cell and cell n are in a l-state and cell n-l and complement cell are in a 0-state, or

(b) said complement cell is in a l-state and said cell n and cell n-l are in a O-state (2) said one cell is reset to a O-state when said cell n, cell n--l and complement cell are in a 1- state, and

13 shift right once gate means connected to each of the binary cells of said accumulator and said Q register for producing a. signal to shift theinforrnation state of the accumulator and Q register or the information state of the summer one bit position to the right in the direction of least significance when (l) cell n, said complement cell and said signal cell are in a l-state and cell n-l and one cell are in a 0-state, or (2) cell n, one cell and complement cell are in a O-state and cell n--l is in a l-state, or (3) cell n-l, one cell, complement cell and said signal cell are in a 1-state and cell n is in a 0- state.

12. The multiplication system of claim 11 in which there is provided a plurality of shift right twice gates connected to each of the binary cells of said accumulator and said Q register and to said one and complement cells for producing a signal to shift the information state of the accumulator and of the Q register of the information state from the summer two bit position to the right in the direction of least significance when (1) cells n and n-l are both in a O-state or both in a l-state, or

0-state.

References Cited UNITED STATES PATENTS Deerfield 23S-164 Keir 23S-164 MacSorley 23S-164 Voltin 23S-164 Coopper et al. 23S-164 Hertz 235-164 MALCOLM A. MORRISON, Primary Examiner D. H. MALZAHN, Assistant Examiner 

